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1. Field of the Invention
The present invention generally relates to a method for semiconductor packaging and assembly, and in particular to a method for creating improved interconnections between a die and package substrate. Still more particularly, the invention relates to a method for creating interconnects with subsequent layers of insulating and conductive materials.
2. Background Information
Modern-day semiconductor devices, commonly called microchips, or xe2x80x9cdie,xe2x80x9d are fabricated on wafers, and the wafers are then sawn into grids, separating the individual chips prior to assembly in a package. Chips are fabricated in a variety of sizes, but typically range from only a few millimeters to a couple of centimeters or more in width. Each chip has numerous electrical signals. Processors, for example, may have several hundred signals. Provisions must be made to electrically connect a die to the component with which it is used (typically, other electrical devices and connections on a printed circuit board) and also to protect the die from damage or other external conditions that could hinder its operation. Package engineering, or packaging, is the field within semiconductor engineering that addresses these needs.
Typically, as a die is designed, a packaging team will assess its layout and other requirements to determine the ideal packaging solution. A myriad of requirements may exist for a particular device, including thermal, reliability, moisture, electrical, package size and cost requirements. As semiconductor devices increase in complexity and shrink in size, packaging them is becoming more and more challenging as a greater numbers of electrical signals and other connections, such as grounds, have to be routed from increasingly smaller chips. As this xe2x80x9cpin countxe2x80x9d increases, new methods must be found to electrically connect the die to the board while continuing to meet increasingly aggressive packaging needs.
Referring now to FIG. 1, signals are typically routed from a die 10 by a ring of substantially square electrical xe2x80x9cbond padsxe2x80x9d 12 located on the edge of the die surface 14. These miniscule bond pads 12 may be less than five one-hundredths of a millimeter (0.05 mm) wide, and spaced just slightly farther apart, to account for surrounding circuitry 16.
Historically, as shown in FIG. 2, chips with a relatively low xe2x80x9cpin count,xe2x80x9d or number of bond pads, have been packaged using xe2x80x9cleadframesxe2x80x9d 20, thin etched or stamped metal frames which have a central area, or flag 22, to which a chip is attached. Referring now to FIG. 3, leadframes 20 generally have metal xe2x80x9cfingersxe2x80x9d 30, pointing inward towards flag 22, which are connected to substantially square electrical xe2x80x9cbond padsxe2x80x9d 12 around the edge of die 10 with hair-like wires 32, which may be 25 thousandths of a millimeter (0.025 mm) or smaller in diameter. This assembly process, called xe2x80x9cwirebonding,xe2x80x9d is performed by extremely precise robotic machines called wirebonders (not shown). FIG. 4 shows a full die 10 wirebonded to a leadframe 20.
As shown in FIG. 5, once the die 10 has been attached to flag 22 by an epoxy 50 or other adhesive and bonded to leadfingers 30 with wires 32, the die 10 is then encapsulated, typically with a solid plastic mold compound 52, or ceramic housing (not shown). Lead fingers 30 then carry the signals out of the edges of the package 54 by doubling as xe2x80x9cfeetxe2x80x9d 56 that are fashioned to contact or pass through specific electrical xe2x80x9clandsxe2x80x9d (not shown) on the board 58.
Several issues exist with peripherally leaded packages. For instance, as all the signals on the die must be routed out the edge of the package, as pin count increases, the footprint of the package may be undesirably forced to increase geometrically since the package area is not utilized for interconnects. Current leaded packages are typically offered in certain predetermined pin counts (such as 100, 112, or 144 leads) with each pin count corresponding to a certain size package (e.g., 10xc3x9710, 14xc3x9714 or 20xc3x9720 mm). For this reason, small increases in the pin count of the die can cause relatively large increases in overall package area, since exceeding the number of pins in one package size would force the die into the next larger package family.
The desire to reduce the size of consumer and other types of electronics (e.g., cell phones, laptop computers, etc.) creates pressure on chip manufacturers to reduce the size of semiconductor packages. Further, a myriad of issues exists with wirebonding, the default interconnect method used with leadframe packages. Referring now to FIG. 6, in the case of plastic packaging, a solid mold compound (not shown) is often unidirectionally injected into the corner of a mold cavity (not shown) around the wirebonded die 10 and spreads out in a pattern 60. The solid mold compound serves to protect the chip and interconnects.
As the mold compound spreads over die 10, it contacts and pushes against wires 32 causing them to bend out or xe2x80x9csweepxe2x80x9d a small distance as shown. For this reason, packaging design guidelines limit wire length and pitch, or the distance between adjacent wires 32, to prevent shorting. For a fine-pitch die, or a die that requires a wire pitch smaller than current high-volume industry standards, and thus, requires a special wirebonder and thinner wires 32, the issue of wire sweep becomes even more troublesome.
Wire sag is also an issue with relatively long or thin wires, which have an inherent sag under their own weight due to their extremely small cross-sections. It is essential that wires do not contact the edges of the die or lead fingers to prevent physical damage. A satisfactory wirebond 32 is shown in FIG. 7A, whereas FIG. 7B shows a drooping wire 32 coming into close contact with the edges of both the die 10 at 72 and lead fingers 30 at 74.
Wirebonding also adds unwanted height to a package 54, since a wirebonding tool (not shown) will typically create a bond by forming a small ball of metal 70 on a bond pad 12 on the edge of die 10, then arc a wire 32 up from ball 70, finally stitching it out to a finger 30 on leadframe 20. For small products, such as cell phones or other popular mobile devices, any added semiconductor package height is undesired.
For these reasons, die with high pin counts or die used in small electronics typically utilize area array packages, one of the most common being the ball grid array (BGA) 80, as shown in FIG. 8A, in which an array of solder balls 82 covers at least part of the bottom surface of a thin, multi-layered board, or substrate 84.
As shown in FIG. 8B, when assembled in a BGA package 80, the die 10 is bonded to the central flag 86 of substrate 84, rather than a metal leadframe. Instead of routing signals from the package periphery down to the board 58 as with a leadframe package, in an area array package, a die 10 may be wirebonded out to conductive xe2x80x9ctracesxe2x80x9d 88 on the substrate 84. These individual traces 88 can pass down through the substrate layers using electrically conductive channels, or vias 89, and down to the bottom layer of the substrate 84, where they are routed to an array of solder balls 82, which serve as interconnects to a matching array on the board 58.
Packaging using substrates 84 affords considerable routing flexibility, as space may be conserved by overlapping different signal traces 88 on different layers of the substrate 84. Further, sensitive signals, which would otherwise interfere with one another if routed out adjacently, may be isolated from one another by surrounding them on the substrate bottom with surplus balls 82.
While area array packaging has met many packaging challenges, the practice of wirebonding still limits the capabilities and features of a packaged device. More advanced methods of attaching a die to a substrate do exist, such as Controlled Collapse Chip Connection (C4) flip-chip packaging, or simply xe2x80x9cflipchip,xe2x80x9d a method in which electrical pads on the top surface of a die are mounted with conductive balls (or xe2x80x9cbumpedxe2x80x9d) then flipped over and bonded top-side-down to similar bumps on the substrate surface.
However, the flipchip process is technically intricate and comparatively expensive, since the bump array on the substrate surface must exactly match that of the die. Also, there is little wiring flexibility, and bumps are difficult to apply to fine-pitch die. These custom, exclusive-use substrates often do not achieve the manufacturing volumes of more generic packaging means, and consequently can be much more expensive. Unlike the exclusive-use substrates used with a flipchip device, the present invention could be used with existing die with peripheral bond pads and existing substrates, without need for custom substrates.
As chip power and pin counts continue to increase and die sizes continue to shrink, thermal and electrical concerns increase concurrently. Removing heat generated by a die is critical in maintaining chip performance, and robust interconnects are needed to adequately handle the electrical output of a high-powered chip. As noted above, it is often desirable to design the smallest die possible. However, occasionally the size and number of bond pads needed for wirebonding around the die edge will force the die to be larger than it otherwise would need to be if, as shown in FIG. 9A, components 90 in the center of the die were small enough to leave unused space between them and the ring of bond pads 12. In this case, staggered rows of bond pads 12, as shown in FIG. 9B, could be used on a die 10, but this solution is often avoided due to reduced wire pitches and greater possibility for wire sweep and shorting. Therefore, a packaging interconnect method is needed that maintains or improves upon the benefits of current packaging technology while addressing one or more of the aforementioned issues.
The problems noted above are solved in large part by a method of creating electrical interconnects between a die and package without the use of wirebonds. Without wirebonds, the problems discussed above are eliminated or at least ameliorated to a great extent. Accordingly, the preferred method is to electrically connect a die and package substrate by applying an electrically non-conducting material over a die, extending onto the package substrate, and leaving a portion of the substrate contact pads exposed. An electrically conductive material is then applied over the non-conductive layer, coming into electrical contact with the die preferably by flowing into holes formed in the insulating layer over the die bond pads or by contacting conductive bumps which are formed on the die bond pads and protrude through the insulating layer. Portions of the conductive layer are then selectively removed to form conductive patches between electrical points of contact on the die and substrate contact pads, respectively. Further, the preferred method entails spraying a layer of conductive ink over an insulating epoxy or polyimide layer, then laser trimming the conductive ink layer to create separate connection traces.